Job Description
Job Description
This is a full-time, on-site role for a Technical Program Manager (ASIC/SoC Design) located in San Jose, CA. The role involves overseeing and managing the lifecycle of ASIC/SoC design projects, ensuring they are completed on time, within scope, and on budget. As a Technical Program Manager, you will serve as the primary bridge between global fabless customers and internal engineering teams. You will lead complex SoC (System-on-Chip) development programs from initial architecture alignment through Final GDSII delivery (Tape-out) and mass production, ensuring technical milestones, project schedules, and business objectives are successfully achieved.
1. Key Responsibilities
•\tProject Lifecycle Management: Lead the end-to-end execution of ASIC design projects, including RTL design, DFT, Synthesis, Physical Design (P&R), and Sign-off (STA, DRC/LVS).
•\tStakeholder Management: Act as the main point of contact for tier-1 fabless customers, foundry partners (e.g., Samsung Foundry), and IP vendors (e.g., Arm, Synopsys).
•\tSchedule & Resource Planning: Develop detailed project timelines and allocate engineering resources across multi-site teams (e.g., Korea, USA, Taiwan) to ensure on-time delivery.
•\tRisk Mitigation: Proactively identify technical bottlenecks in advanced nodes (2nm/4nm) and implement contingency plans to avoid schedule slips.
•\tTechnical Alignment: Moderate technical discussions regarding power, performance, area (PPA) trade-offs, and advanced packaging requirements (2.5D/3D, HBM, Chiplets).
•\tFinancial Oversight: Manage project budgets, NRE (Non-Recurring Engineering) costs, and invoicing milestones.
2. Qualifications & Requirements
Technical Expertise
•\tEducational Background: B.S. or M.S. in Electrical Engineering, Computer Science, or a related technical field.
•\tIndustry Experience: 7+ years of experience in the semiconductor industry, with a proven track record of managing high-performance SoC projects.
•\tDesign Flow Knowledge: Deep understanding of the RTL-to-GDSII flow, including timing closure, power analysis, and physical verification.
•\tAdvanced Node Experience: Hands-on experience or strong familiarity with FinFET/GAA processes and advanced packaging technologies (UCIe, CoWoS, etc.).
Professional Skills
•\tCommunication: Excellent verbal and written communication skills in English.
•\tLeadership: Ability to lead cross-functional teams without direct authority and manage conflict in high-pressure environments.
•\tTools: Proficiency in project management software (Jira, Confluence, Microsoft Project) and familiarity with EDA tool capabilities.
3. Preferred Qualifications
•\tFoundry Experience: Previous experience working within a Foundry (Samsung, TSMC) or a major DSP (Design Solution Partner) ecosystem.
•\tMarket Insight: Knowledge of specific high-growth sectors such as AI/HPC, or Automotive.
Benefits
•\tMedical, Dental, and Vision Coverage
•\t401(k) Retirement Plan with Company Matching
•\tPaid Time Off (PTO) and Company Holidays
•\tOn-site Fitness Center Access
•\tCollaborative and Global Team Environment
•\tCareer Growth Opportunities within a Global Semiconductor Company
CoAsia SEMI USA is an Equal Opportunity Employer. We are committed to fostering a diverse and inclusive workplace. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, national origin, age, disability, protected veteran status, or any other characteristic protected by applicable federal, state, or local laws.