Senior Design Verification Engineer
Job Description
We're working with a well-funded, highly selective AI infrastructure startup building silicon for large-scale AI inference and training. Founded by veteran chip architects who previously led a major AI hardware program at a top tech company, the business has grown fast and is backed by top-tier investors.
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They're looking for a silicon verification engineer to help build best-in-class silicon for high-performance, sustainable GenAI, across compute, memory management, and high-speed connectivity.
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The Role
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The design and verification environment here is genuinely unusual: a custom, code-generated cycle-accurate model sits at the center of the flow, feeding architecture validation, RTL validation, and post-silicon validation, with hardware description largely generated from this model rather than handwritten. The team is also building AI directly into the design flow itself (retrieval, knowledge-graph, and automated-reasoning tooling). You'd help build and extend this model and tooling, alongside more traditional verification work. Responsibilities aren't fixed, and they're looking for versatile engineers.
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Responsibilities
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- Contribute to verification methodology with a scalable solution across blocks, subsystems, full-chip and system-level validation
- Own portions of verification execution at subsystem and chip level, building testbenches, tests and related artefacts to achieve structural and functional coverage closure
- Plan and drive intermediate and sign-off reviews on verification test plans, execution progress and closure towards key silicon milestones, including design freeze and tapeout
- Help build and extend the core modelling and verification tooling that underpins the whole design flow
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Requirements
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- Concept-to-silicon experience, driving verification from an architecture or design spec through to production silicon
- Experience with SystemVerilog, Python, C/C++, and comfort picking up newer languages (e.g. Rust, Bluespec, Haskell) for verification and silicon modelling
- Production experience with advanced verification methodologies such as UVM and assertion-based verification (ABV); comfort with both formal and simulated verification
- Production experience creating portable tests and drivers that apply to silicon validation and post-silicon debug
- Strong understanding of silicon micro-architecture in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, and memory management
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Nice to have
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- Familiarity with emulation and prototyping platforms and methodologies
- Hands-on experience with silicon debug and bring-up
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What Sets This Role Apart
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- Tool-building culture: the verification flow is built largely in-house, generated from a custom modelling layer rather than relying on legacy, vendor-driven methodology
- AI-native flow: active work integrating AI tooling (retrieval, knowledge graphs, automated reasoning) directly into design and verification
- Real ownership: your work feeds directly into production silicon at a company scaling fast
- Flexible scope: significant freedom to shape what you work on, from core modelling and tooling through to deeper architecture involvement
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Package & Process
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Compensation is highly competitive, with strong equity and full benefits. Primarily in-person, with some flexibility for remote depending on the candidate.