<h3>Job Description</h3>
Job Description
Job Title: DFT Engineers (9 Positions)
Location: Santa Clara, CA (Hybrid)
Rate: $70/hr on C2C or 1099
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Job Description:
<ul>
<li>5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs</li>
<li>Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing</li>
<li>Proven expertise in ATPG pattern generation, analysis, and debug</li>
<li>Experience with MBIST, including memory test architectures and diagnostics</li>
<li>Knowledge of IO Test methodologies for interface and pin level validation</li>
<li>Solid understanding of clock DFT and clock verification concepts</li>
<li>Strong grasp of digital design and RTL fundamentals</li>
<li>Experience with industry standard DFT/ATPG EDA tools</li>
<li>Ability to work effectively in fast paced, high performance semiconductor programs</li>
<li>Strong analytical, problem solving, and communication skills</li>
</ul>