Physical IC Layout Engineer - Analog / PMIC

Job Description

Job DescriptionAbout the Role

We are seeking an experienced Physical IC Layout Engineer to join our growing US-based High-Performance Computing & Edge AI Power team.

This role focuses on full-chip and block-level analog/power IC layout while serving as a key technical liaison between our US design engineers and China-based layout team.

You will contribute to next-generation power management solutions for AI data centers, high-performance computing, and advanced power delivery applications.

Key Responsibilities

• Design and implement full-chip and block-level physical layouts for analog, mixed-signal, and power management ICs (PMICs).
• Perform device placement and metal routing, optimizing matching, symmetry, parasitics, current density, and thermal performance.
• Execute DRC, LVS, and ERC verification, resolving layout issues to ensure manufacturability.
• Collaborate closely with analog and digital design engineers to ensure layout quality and design integrity.
• Serve as the primary technical liaison between US and China engineering teams, facilitating design reviews and technical discussions in English and Mandarin.
• Support layout development across 55nm–90nm process technologies.

Qualifications

• 5+ years of hands-on IC layout experience in analog, mixed-signal, or power management IC design.
• Experience with both full-chip and block-level layout.
• Hands-on experience with 55nm–90nm process nodes (Required).
• Fluent in English and Mandarin Chinese (Required), with strong technical communication skills.
• Proficiency in Cadence Virtuoso and Calibre or equivalent DRC/LVS/ERC verification tools.
• Strong understanding of device matching, guard rings, deep N-well, ESD/latch-up, electromigration, and layout-dependent effects.
• Ability to collaborate across global engineering teams and independently manage technical challenges.

Preferred Qualifications

• Experience with 130nm or 180nm process technologies.
• Familiarity with DC-DC converters, switching regulators, multiphase controllers, or power management IC architectures.
• Previous experience coordinating layout development across geographically distributed teams.