Job Description
Job Description
Job Summary
We are looking for a skilled DFT/ATPG Engineer with 5 years of hands-on experience in ASIC/SoC design and manufacturing test. The candidate should have strong knowledge of DFT fundamentals, ATPG, scan-based testing, MBIST, IO testing, and clock DFT. The role involves developing, analyzing, and debugging DFT/ATPG solutions and working closely with cross-functional semiconductor teams.
Roles & Responsibilities
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Develop and implement DFT solutions for ASIC/SoC designs.
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Perform scan insertion, scan-chain verification, and DFT rule checks.
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Generate, analyze, and debug ATPG patterns.
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Improve fault coverage and analyze ATPG coverage reports.
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Work with stuck-at, transition, and other relevant fault models.
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Support MBIST implementation, memory testing, and diagnostics.
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Work on IO test methodologies and pin-level validation.
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Support clock DFT implementation and clock verification.
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Debug DFT, ATPG, scan-chain, and simulation issues.
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Collaborate with RTL, Design, Verification, Physical Design, and Test teams.
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Use industry-standard DFT/ATPG EDA tools.
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Support DFT verification, signoff, and post-silicon debug activities.
Experience Level
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5 years of hands-on experience in DFT and ATPG for ASIC/SoC designs.
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Strong experience in scan, ATPG, MBIST, IO testing, and clock DFT.
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Experience with industry-standard DFT/ATPG EDA tools.
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Good scripting/debugging skills are preferred.
Education
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Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
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Strong understanding of digital design and RTL fundamentals.