<h3>Job Description</h3>
Job Description DFT Engineers Location: Santa Clara, California Type: Contract Work Arrangement: Onsite Number of Openings: 9 Job Description &amp; Skill Requirement Required Skills &amp; Qualifications •&nbsp; &nbsp; &nbsp; 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs. •&nbsp; &nbsp; &nbsp; Strong understanding of DFT fundamentals, including controllability, observability, and scan-based testing. •&nbsp; &nbsp; &nbsp; Proven expertise in ATPG pattern generation, analysis, and debug. •&nbsp; &nbsp; &nbsp; Experience with MBIST, including memory test architectures and diagnostics. •&nbsp; &nbsp; &nbsp; Knowledge of IO test methodologies for interface- and pin-level validation. •&nbsp; &nbsp; &nbsp; Solid understanding of clock DFT and clock verification concepts. •&nbsp; &nbsp; &nbsp; Strong grasp of digital design and RTL fundamentals. •&nbsp; &nbsp; &nbsp; Experience with industry-standard DFT/ATPG EDA tools. •&nbsp; &nbsp; &nbsp; Ability to work effectively in fast-paced, high-performance semiconductor programs. •&nbsp; &nbsp; &nbsp; Strong analytical, problem-solving, and communication skills. Qualification •&nbsp; &nbsp; &nbsp; Bachelor of Engineering (BE)