Staff Design Engineer | Multi-GPU/TPU NoC & Fabric Architecture
Job Description
Staff Design Engineer | Multi-GPU/TPU NoC & Fabric Architecture
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Oxmiq Labs | Bay Area, US (On-site)
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About OXMIQ
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OXMIQ designs GPU and AI silicon for large-scale model inference and training, and is building the system software and analysis platforms that prove out those designs before they reach customers. We are a startup driving innovation across the full stack — from atoms to agents — and we move fast on the strength of our own tools.
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About the Role
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We are seeking an experienced Staff Design Engineer to architect and design the next generation of high-performance interconnects for scalable AI computing systems. You will play a key role in defining the on-chip and multi-chip communication fabric that enables efficient scaling across GPU, TPU, and AI accelerator clusters.
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Key Responsibilities
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- Design scalable Network-on-Chip (NoC) and fabric solutions for multi-GPU, TPU, and AI accelerator systems
- Define low-latency, high-bandwidth communication architectures supporting hundreds to thousands of compute cores.
- Design cache-coherent and non-coherent interconnect protocols for compute, memory, and I/O subsystems.
- Develop routing algorithms, QoS mechanisms, congestion management, flow control, and deadlock avoidance techniques.
- Define memory hierarchy interactions involving HBM, shared memory, L2 cache, PCIe, CXL, and coherent interconnects.
- Collaborate with architecture, compiler, runtime, and software teams to optimize communication for AI training and inference workloads.
- Drive microarchitecture specifications, RTL design reviews, and performance modeling.
- Work closely with verification teams to develop architecture-level validation plans and performance benchmarks.
- Analyze workload behavior and identify bottlenecks in large-scale distributed AI systems.
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Required Qualifications
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- 10+ years of experience in ASIC or SoC architecture and design.
- Deep understanding of Network-on-Chip (NoC) architectures, including meshes, torus, rings, crossbars, hierarchical NoCs, or custom fabrics.
- Experience designing communication fabrics for GPUs, TPUs, AI accelerators, HPC processors, or high-performance SoCs.
- Strong knowledge of cache coherency protocols, memory consistency models, and memory hierarchy design.
- Experience with high-speed interconnect technologies such as PCIe, CXL, UCIe, NVLink, Infinity Fabric, or similar technologies.
- Experience with performance modeling and architectural simulation.
- Strong RTL design experience using Verilog or SystemVerilog.
- Excellent debugging and cross-functional collaboration skills.
- Experience with large-scale AI training systems and distributed machine learning.
- Experience with HBM memory systems, memory controllers, and coherence fabrics.
- Experience with virtualization technologies including IOMMU, ATS, Address Translation Cache (ATC), and shared virtual memory.
- Experience with formal verification, emulation, FPGA prototyping, or silicon bring-up.
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Education
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- BS, MS, or PhD in Computer Engineering, Electrical Engineering, or Computer Science.
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Working Environment
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This is a hands-on role working closely with architecture, compiler, runtime, software, and verification teams to define and validate the interconnect fabric powering OXMIQ's multi-GPU/TPU AI systems. The Staff Design Engineer collaborates cross-functionally from microarchitecture specification through RTL design review and silicon validation. AI-assisted development tools (Claude Code or equivalent) are a standard part of engineering practice at OXMIQ and are expected in daily work.
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Compensation & Benefits
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OXMIQ offers a competitive compensation package, including base salary, equity participation, comprehensive medical, dental, and vision coverage, and the opportunity to contribute to foundational silicon and software technology.
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OXMIQ is an equal opportunity employer. We evaluate qualified applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected characteristic.